Leakage current correcting circuit

ABSTRACT

A leakage current correcting circuit for reducing a leakage current flowing into an output of a circuit in a high impedance state. The configuration includes a correcting unit having a current detecting circuit for detecting a leakage current and outputting a current equal to a detected leakage current, and a current supply circuit for receiving the output current from the current detecting circuit as an input and causing a current for offsetting the leakage current flowing into the output of the circuit in a high impedance state.

TECHNICAL FIELD

The present invention relates to a semiconductor testing apparatus fortesting a semiconductor device, and more particularly to a leakagecurrent correcting circuit for reducing a leakage current in aprogrammable load circuit or the like which acts as a load for a deviceunder test.

BACKGROUND ART

An electronic circuit on the test head of a semiconductor testingapparatus dedicated to input/output pins of a device under test(hereinafter referred to as “DUT”) is called pin electronics. The pinelectronics comprises a driver for applying a predetermined signal tothe pins of a DUT, a comparator for determining the level of a signal(High or Low) outputted from the DUT, and a programmable load circuitwhich acts as a load when a signal is outputted from the DUT.

A load condition for the programmable load circuit may be changed by aprocessor for controlling the entire semiconductor testing apparatus,and any load may be created as defined in the specifications of a DUT.

FIG. 1 is a circuit diagram showing an exemplary configuration of aprogrammable load circuit.

In FIG. 1, pin electronics comprise driver 3, comparator 4, andprogrammable load circuit 1, to which DUT 2 is connected for conductinga test.

Programmable load circuit 1 comprises a diode bridge composed of fourdiodes D3-D6; first current source 14 and second current source 15acting as loads for DUT 2; programmable voltage source 20 for applyingto the diode bridge threshold voltage Vth which serves as a decisionstandard for selecting first current source 14 or second current source15, both of which act as loads for DUT 2; transistors Q5-Q8 serving asswitches for connecting first current source 14 and second currentsource 15 to the diode bridge or to a ground potential; first regulatedvoltage source 18 (negative voltage source) for discharging node A whenprogrammable load circuit 1 is OFF; second regulated voltage source 19(positive voltage source) for charging node B when programmable loadcircuit 1 is OFF; diode D1 serving as a switch for connecting node Awith first regulated voltage 18; diode D2 serving as a switch forconnecting node B with second regulated voltage source 19; ON/OFF signalsource 11 for outputting a signal for controlling programmable loadcircuit 1 to turn ON/OFF; third current source 16 for drawing a voltageat node B into output voltage Vp of second regulated voltage source 19when programmable load circuit 1 is OFF; fourth current source 17 fordrawing a voltage at node A into output voltage Vm of first regulatedvoltage source 18 when programmable load circuit 1 is OFF; transistorsQ1-Q4 serving as switches for switching current paths of third currentsource 16 and fourth current source 17; and first level shift circuit 12and second level shift circuit 13 for driving transistors Q1-Q8 inaccordance with an output signal of ON/OFF signal source 1.

The ON of programmable load circuit 1 refers to a state in which firstcurrent source 14 or second current source 15 is connected to DUT 2 as aload, whereas the OFF of programmable load circuit 1 refers to a statein which first current source 14 and second current source arerespectively connected to the ground potential and no load is connectedto DUT 2.

Also, output voltage Vth of programmable voltage source 20, outputcurrent I₁ of first current source 14, and output current I₂ of secondcurrent source 15 are each variable, and are set to predetermined valueswith programming processing.

In such a configuration, when a signal is outputted from DUT 2, theoutput of driver 3 is maintained in a high impedance state, andprogrammable load circuit 1 is set ON. Programmable load circuit 1 isON/OFF controlled by an output signal of ON/OFF signal source 11 suchthat it turns ON when a signal at High level is outputted from ON/OFFsignal source 11.

When a signal at High level is outputted from ON/OFF signal source 11,first level shift circuit 12 supplies a base current to transistors Q1and Q6, while second level shift circuit 13 supplies a base current totransistors Q3 and Q8. At this time, transistors Q2, Q4, Q5, Q7 are OFF,while transistors Q1, Q3, Q6, Q8 turn ON.

When transistors Q1 and Q3 turn ON, third current source 16 and fourthcurrent source 17 are connected to the ground potential throughtransistors Q1 and Q3, respectively.

When a signal at High level is outputted from DUT 2 in such a state,current I₂ flows from DUT 2 to second current source 15 through diode D6since the output voltage of DUT 2 is a voltage higher than thresholdvoltage Vth.

On the other hand, when a Low level is outputted from DUT 2, current I₁flows from first current source 14 to DUT 2 through diode D4 since theoutput voltage of DUT 2 is a voltage lower than threshold voltage Vth.

Therefore, a load connected to the output of DUT 2 is switched inaccordance with its output voltage and the value of the load isdetermined by current value I₁ of first current source 14 and currentvalue I₂ of second current source 15.

Since programmable voltage source 20, first current source 14, andsecond current source 15 may respectively change their output valueswith programming processing, current values I₁, I₂, which act as loads,may be changed in accordance with the specifications of DUT 2.

On the other hand, when DUT 2 is switched into a signal input state, asignal is outputted from driver 3 to DUT 2, and the output of DUT 2 isset in a high impedance state. Additionally, since no load needs to beconnected, programmable load circuit 1 is set OFF.

Programmable load circuit 1 turns OFF when a signal at Low level isoutputted from ON/OFF signal source 11. When a Low level is outputtedfrom ON/OFF signal source 11, first level shift circuit 12 supplies abase current to transistors Q2 and Q5, while second level shift circuit13 supplies a base current to transistors Q4 and Q7. In this event,transistors Q1, Q3, Q6, Q8 are OFF respectively, and transistors Q2, Q4,Q5, Q6 turn ON respectively.

When transistors Q2 and Q4 turn ON, third current source 16 and node Bare connected through transistor Q2 to charge a parasitic capacitance atnode B to (Vp plus forward voltage V_(F) of diode D2).

Additionally, fourth current source 17 and node A are connected throughtransistor Q4 to discharge a parasitic capacitance at node A to (Vmminus forward voltage V_(F) of diode D5).

On the other hand, when transistors Q5, Q7 turn ON, first current source14 is connected to the ground potential through transistor Q5, whilesecond current source 15 is connected to the ground potential throughtransistor Q7. Thus, connection of DUT 2 with first current source 14and second current source 15, which act as loads therefore, isdisconnected.

In such a programmable load circuit and driver having the pinelectronics, it is desirable that leakage current be smaller to providemore accurate testing in an output disabled state.

With programmable load circuit 1 shown in FIG. 1, leakage currentI_(leakage) is expressed as I_(leakage)=I_(D4)-I_(D6) in the disabledstate, i.e., when programmable load circuit 1 is OFF.

The programmable load circuit shown in FIG. 1 is a circuit which setsthe output in a high impedance state by backwardly biasing a diode or atransistor. When high speed diodes, transistors or the like are used insuch a circuit, the leakage current is increased by backward biasingbecause of the general tendency that faster devices exhibit a lowerbackward withstand voltage.

For this reason, when the source current (current consumed) of DUT 2 ismeasured, leakage current of the pin electronics affects the respectivepins of DUT 2, causing a deterioration of the measuring accuracy of asemiconductor testing apparatus.

The present invention has been made to solve the aforementioned inherentproblem in the prior art, and it is an object to provide a leakagecurrent correcting circuit which is capable of reducing a leakagecurrent which flows into an output of a programmable load circuit or adriver in order to improve the measuring accuracy of a semiconductortesting apparatus.

DISCLOSURE OF THE INVENTION

The present invention relates to a leakage current correcting circuitfor reducing a leakage current which flows into an output of a circuitin a high impedance state, wherein the leakage current correctingcircuit is constructed to have a correcting circuit for detecting aleakage current and cause a current to flow for offsetting the leakagecurrent flowing into the output of the circuit.

In this way, the leakage current flowing into the output of the circuitis offset by the current outputted from the correcting circuit, therebymaking it possible to reduce the leakage current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an exemplary configuration of aprogrammable load circuit;

FIG. 2 is a circuit diagram showing a configuration of a leakage currentcorrecting circuit according to the present invention;

FIG. 3 is a circuit diagram showing a configuration of a firstembodiment of the leakage current correcting circuit according to thepresent invention;

FIG. 4 is a circuit diagram showing a configuration of a secondembodiment of the leakage current correcting circuit according to thepresent invention; and

FIG. 5 is a circuit diagram showing another exemplary configuration of acurrent mirror circuit included in the leakage current correctingcircuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Next, the present invention will be described with reference to thedrawings.

FIG. 2 is a circuit diagram showing a configuration of a leakage currentcorrecting circuit according to the present invention. FIG. 2 shows aconfiguration in which the leakage current correcting circuit accordingto the present invention is added to driver 3 shown in FIG. 1.

In FIG. 2, driver 3 comprises transistors Q11 and Q12 for applying apredetermined signal to DUT 2; diodes D11 and D12 connected in serieswith transistors Q11 and Q12; first switch 34 for switching a voltageapplied to the base of transistor Q1; second switch 35 for switching avoltage applied to the base of transistor Q12; first regulated voltagesource 36 for applying negative voltage Vm to the base of transistor Q11when driver 3 is OFF to turn transistor Q11 OFF; second regulatedvoltage source 37 for applying positive voltage Vp to the base oftransistor Q12 when driver 3 is OFF to turn transistor Q12 OFF; firstlevel shift circuit 32 for applying a driving voltage to the base oftransistor Q11 when driver 3 is ON; second level shift circuit 33 forapplying a driving voltage to the base of transistor Q12 when driver 3is ON; and third switch 31 for switching voltages applied to first levelshift circuit 32 and second level shift circuit 33.

Driver 3 is connected to third regulated voltage source 23 for supplyinga High level voltage applied to first level shift circuit 32 and secondlevel shift circuit 33; fourth voltage source 24 for supplying a Lowlevel voltage; H/L signal source 22 for outputting a signal forswitching third switch 31 of driver 3; and ON/OFF signal source 21 foroutputting a signal for controlling driver 3 to turn ON/OFF. Driver 3 iscontrolled by these circuits.

In such a configuration, when driver 3 is OFF, i.e., in a disabledstate, transistors Q11 and Q12 are OFF, so that the output of driver 3is in a high impedance state. At this time, it is desirable that theleakage current flowing into the output be smaller. However, leakagecurrent I_(leakage) actually flows through diodes D11, D12 andtransistors Q11, Q12, and its value is expressed by:

I_(leakage)=I_(D11)-I_(D12)

The leakage current correcting circuit according to the presentinvention comprises first correcting circuit 51 for correcting a leakagecurrent flowing through diode D11, and second correcting circuit 52 forcorrecting a leakage current flowing through diode D12.

First correcting circuit 51 detects current I_(D11) flowing throughdiode D11, and has current I_(out1) having a current value equal toI_(D11) and the opposite polarity flow into the output of driver 3.

Similarly, second correcting circuit 52 detects current I_(D12) flowingthrough diode D12, and has current I_(out2) having a current value equalto I_(D12) and the opposite polarity flow into the output of driver 3.

In this event, a leakage current I_(leakage) flowing into the output ofdriver 3 is:

I_(leakage)=I_(D11)−I_(out1)−I_(D12)+I_(out2)=0

Thus, the measuring accuracy of the semiconductor testing apparatus isimproved since the leakage current, viewed from DUT 2, can be reduced.

Next, the present invention will be described more specifically withreference to embodiments.

(First Embodiment)

FIG. 3 is a circuit diagram showing a configuration of a firstembodiment of the leakage current correcting circuit according to thepresent invention. In this embodiment, a specific example of a circuitwill be illustrated for the leakage current correcting circuit added todriver 3 shown in FIG. 2.

In FIG. 3, the leakage current correcting circuit according to theembodiment comprises first correcting circuit 51 for correcting aleakage current flowing into diode D11 of driver 3, and secondcorrecting circuit 52 for correcting a leakage current flowing throughdiode D12 of driver 3.

First correcting circuit 51 includes a first current mirror circuit 54which is formed from transistors Q13 and Q14 and receives leakagecurrent I_(D11) flowing through diode D11 to output a current equal toI_(D11); and a second current mirror circuit 53 which is formed fromtransistors Q15 and Q16 and receives the current outputted from firstcurrent mirror circuit 54 for causing current I_(out) having theopposite polarity to leakage current I_(D11) flow into the output ofdriver 3.

Second correcting circuit 52 includes a third current mirror circuit 55which is formed from transistors Q17 and Q18 and receives a leakagecurrent I_(D12) flowing into diode D12 to output a current equal toI_(D12); and a fourth current mirror circuit 56 which is formed fromtransistors Q19 and Q20 and receives the current outputted from thirdcurrent mirror 55 for causing current I_(out2) having the oppositepolarity to leakage current I_(D12) flow into the output of driver 3.

Next, the operation of the leakage current correcting circuit will bedescribed in the configuration shown in FIG. 3.

When driver 3 is in a disabled state, backward voltages are appliedacross diode D11 and the base-to-mitter of transistor Q11 respectivelysince negative voltage Vm is applied to the base of transistor Q11. Atthis time, backward current I_(D11) (leakage current) flows throughdiode D11, while backward current I_(Q11) flows through the base-emitterof transistor Q11.

Since the backward voltage applied across the base-emitter of transistorQ11 is limited to approximately 0.7 volts which is a forward voltageacross the base-emitter of transistor Q13 in first current mirrorcircuit 54, the value of I_(Q11) becomes extremely small and it isnegligible. In other words:

I_(D11)=I_(Q13)+I_(Q11≈I) _(Q13)

Since first current mirror circuit 54 and second current mirror 53respectively operate to equalize input and output currents, I_(Q13)which is the input current to first current mirror circuit 54, I_(Q14)which is the output current for first current mirror circuit 54 and theinput current for second current mirror circuit 53, and I_(out1) whichis the output current from second current mirror circuit 53 respectivelyhave equal values.

Thus, current I_(D11) flowing through diode D11 and output currentI_(out1) from first correcting circuit 51 have equal current values andopposite polarities, as shown in FIG. 3.

Similarly, I_(Q17) which is the input current of third current mirrorcircuit 55 in second correcting circuit 52, I_(Q18) which is the outputcurrent from third current mirror circuit 55 and the input current tofourth current mirror circuit 56, and output current I_(out2) for fourthcurrent mirror circuit 56 respectively have equal values, so thatcurrent I_(D12) flowing through diode D12 and output current I_(out2) ofsecond correcting circuit 52 have equal current values and oppositepolarities, as shown in FIG. 3.

Thus, the leakage current I_(leakage) of driver 3, viewed from DUT 2, isexpressed by:

I_(leakage)=I_(D11)−I_(out1)−I_(D12)+I_(out2)=0

(Second Embodiment)

FIG. 4 is a circuit diagram showing a configuration of a secondembodiment of the leakage current correcting circuit according to thepresent invention. The leakage current correcting circuit according tothis embodiment has a configuration in which the leakage currentcorrecting circuit according to the present invention is added to theprogrammable load circuit shown in FIG. 1.

In FIG. 4, the leakage current correcting circuit according to theembodiment comprises first correcting circuit 61 for correcting aleakage current flowing into diode D4 of programmable load circuit 1;and second correcting circuit 62 for correcting a leakage currentflowing into diode D6 of programmable load circuit 1.

First correcting circuit 61 includes diode D21 having the samecharacteristic as that of diode D4 in programmable load circuit 1;transistor Q21 which has its emitter connected to node A through diodeD21 and into which a current equal to current I_(D4) flowing throughdiode D4 flows; first current mirror circuit 63 which receives currentI_(Q21) flowing through transistor Q21 as an input current to outputcurrent I_(Q24) equal to input current I_(Q21); and transistor Q22 whichreceives output current I_(Q24) from first current mirror circuit 63 asan input to have current I_(Q22) equal to I_(Q24) flow into an output(node C) of programmable load circuit 1.

Second correcting circuit 62 comprises diode D22 having the samecharacteristic as that of diode D6 in programmable load circuit 1;transistor Q25 which has its emitter connected to node B through diodeD22 and into which a current equal to current I_(D6) flowing throughdiode D6 flows; second current mirror circuit 64 which receives currentI_(Q25) flowing through transistor Q25 as an input current to outputcurrent I_(Q28) equal to input current I_(Q25); and transistor Q26 whichreceives output current IQ₂ 8 of second current mirror circuit 64 tohave current I_(Q26) equal to IQ₂₈ flow into the output (node C) ofprogrammable load circuit 1.

Next, the operation of the leakage current correcting circuit will bedescribed in the configuration illustrated in FIG. 4.

When programmable load circuit 1 is in a disabled state, since Vm−(forward voltage V_(F) of diode D1) is applied to node A, a backwardvoltage is applied to diode D4, causing backward current (leakagecurrent) I_(D4) to flow therethrough. In this event, the backwardvoltage applied to diode D4 is equally applied to diode D21, so thatI_(D4)=I_(D21) stands.

Assuming that transistor Q21 has sufficiently large h_(FE) and a basecurrent of transistor Q21 is negligible, I_(D21)=I_(Q21) stands.

First current mirror circuit 63 outputs current I_(Q24) substantiallyequal to I_(Q21), and transistor Q22 has current I_(Q22) substantiallyequal to I_(Q24) flow into node C. In other words, I_(D4)=I_(Q22) stands(however, as shown in FIG. 4, I_(D4) and I_(Q22) are opposite inpolarity).

Similarly, since Vp+ (forward voltage V_(F) of diode D2) is applied tonode B, a backward voltage is applied to diode D6, causing leakagecurrent I_(D6) to flow therethrough. At this time, the backward voltageapplied to diode D6 is equally applied to diode D22, so thatI_(D6)=I_(D22) stands.

Assuming that transistor Q25 has sufficiently large h_(FE), and a basecurrent of transistor Q25 is negligible, and I_(D22)=I_(Q25) stands.

Second current mirror circuit 64 outputs current I_(Q28) substantiallyequal to I_(Q25), and transistor Q26 has current I_(Q26) substantiallyequal to I_(Q28) flow into node C. In other words, I_(D6)=I_(Q26) stands(however, as shown in FIG. 4, I_(D6) and I_(Q26) are opposite inpolarity).

Thus, leakage current I_(leakage) of programmable load circuit 1, viewedfrom DUT 2, is expressed by:

I_(leakage)=I_(D4)−I_(Q22)−I_(D6)+I₂₆=0

The respective current mirror circuits shown in FIG. 3 and FIG. 4 showthe simplest configurations. The respective current mirror circuits arenot limited to these configuration, and with the use of a known currentmirror circuit capable of reducing the influence of a base current asshown in FIG. 5, it is possible to provide a leakage current correctingcircuit which further reduces errors. Additionally, each of diodes D11,D12 shown in FIG. 3 and diodes D1-D6, D21, D22 shown in FIG. 4 may bereplaced with a circuit which has a transistor having its base and itscollector connected to each other.

INDUSTRIAL APPLICABILITY

The leakage current correcting circuit according to the presentinvention is useful in a circuit which sets an output in a highimpedance state by backwardly biasing a diode or a transistor, and isparticularly suitable for a driver or a programmable load circuit in pinelectronics for a semiconductor testing apparatus.

What is claimed is:
 1. A leakage current correcting circuit for reducinga leakage current flowing into an output of a tri-state driver,comprising: a correcting unit for detecting the leakage current andcausing a current to flow for offsetting said leakage current flowinginto the output of the driver; wherein: said correcting unit includes: acurrent detecting circuit for detecting the leakage current andoutputting a current equal to the leakage current; and a current supplycircuit for receiving the output current from said current detectingcircuit as input and causing a current to flow for offsetting saidleakage current flowing into the output of said driver; and said currentdetecting circuit is a current mirror circuit.
 2. The leakage currentcorrecting circuit according to claim 1, wherein said current supplycircuit is a current mirror circuit.
 3. A leakage current correctingcircuit for reducing a leakage current flowing into an output of acircuit in a high impedance state, comprising: a correcting unit fordetecting the leakage current and causing a current to flow foroffsetting said leakage current flowing into the output of the circuit,wherein: said correcting unit includes: a first circuit for detectingthe leakage current and outputting a current equal to the leakagecurrent; a second circuit for receiving the output current from saidfirst circuit as input for outputting a current having the oppositepolarity to that of the output current; and a third circuit forreceiving the output current from said second circuit as an input andcausing a current to flow for offsetting said leakage current flowinginto the output of said circuit; and said first circuit includes: adiode through which a current equal to the leakage current flows; and atransistor having an emitter connected in series to said diode, and acollector from which a current equal to the leakage current isoutputted.
 4. The leakage current correcting circuit according to claim3, wherein said second circuit is a current mirror circuit.
 5. Theleakage current correcting circuit according to claim 3, wherein saidthird circuit includes: a transistor having a base and a collectorconnected in common, said transistor receiving the output current fromsaid second circuit to output from an emitter thereof a current foroffsetting said leakage current.